1. Field of the Invention
The invention relates to a sense amplifier configuration for a semiconductor memory device.
Modern semiconductor memory devices have a memory area with a plurality of memory elements or memory cells. The memory elements or memory cells in this case are often produced in a matrix-like configuration and can be addressed via access lines or access lines, for example “bit lines” or “word lines”, in order to read and/or to change the memory state or information state of each memory element or of each memory cell.
In this case, addressing and hence access are normally effected using corresponding selection devices on the basis of a row selection, for example for the word lines, and through a column selection, for example for the bit lines. In this context, the system of memory cells configured in matrix form and of the selected and unselected access lines forms a network of nonreactive resistances, with the cell resistances of the individual memory elements or memory cells needing to be taken into account, in particular.
The selection of a corresponding word line and of a corresponding bit line is intended, particularly when reading, to address precisely one well-defined memory cell or one well-defined memory element. Due to the network-like interconnection of the plurality of memory cells in the memory area, however, not only the signal which represents the memory state or information state of the addressed cell but also parasitic signals from the unselected memory elements or memory cells arise and/or access lines which are superimposed on the selected cell's signal which is actually to be detected and analyzed and can result in corruptions.
To suppress these parasitic signals or to minimize them, a sense amplifier is normally used that allows the selected memory area to be isolated from the unselected memory area and the corresponding signals. By way of example, in the case of MRAM storage on cross-point basis, where the memory state or information state of a memory cell is discriminated on the basis of the size of a cell current which is to be detected, a device is provided which sets the potential difference across the unselected memory area such that the current flowing through this unselected memory area does not decisively influence the detection of the cell current which is actually to be evaluated. In this case, by way of example, “compensation voltage source devices” are used which are produced in the sense amplifier configurations, in particular.
A problem in this context is that, under real conditions, the amplifiers used in this case produce a finite, often also varying voltage offset and additionally have only a finite gain. As a result, the control difference means that parasitic signals still arise that are produced and/or supplied by the unselected memory cells on the corresponding bit line.
To overcome this problem, it has to date been possible to use only conventional methods of offset compensation. Prior-art offset compensation circuits operate slowly, however, and require comparatively large areas on the semiconductor layout.